This invention concerns a system for reducing phase fluctuations or jitter in synchronous digital transmission systems in which demultiplexing is done of a group of binary channels with a determined transmission rate, also termed tributaries, starting from a single binary channel of higher order in the digital hierarchy. The tolerances in the clock frequencies that determine the transmission rates of each of the tributary channels as well as the one of the channel of higher hierarchy require the use of certain justification mechanisms during the process of tributary multiplexing, and of frequency adjustment in some of the clocks of these tributaries when they are being demultiplexed.
It is of special application in the demultiplexing of tributary channels in the SONET and in the Synchronous Digital Hierarchy when extracting the tributary channels from the corresponding channel of higher order in the digital hierarchy when there are strict limitations in the value of jitter in any of the tributary channels in question.
In synchronous digital transmission systems, channels at a determined data rate are combined or multiplexed to form a channel of higher order in the digital hierarchy. This channel of higher hierarchical order is formed, for each frame, by a frame of each tributary plus additional information termed the path overhead in which are included justification bits that permit the absorption of excessive or insufficient net information streams in the incoming frames of each tributary, produced as a result of the clock tolerances of each channel.
These bits are obtained by justification mechanisms, normally of bits or bytes, that compensate for the excess of input information of the corresponding tributary channel by means of negative justification, consisting of transmitting the excess information bits of the tributary in what are termed justification bits and indicating this situation with other justification control bits. In a similar manner, when there is insufficient input information in a tributary channel, positive justification is done, which basically consists of marking certain bits, which normally carry information, as vacant.
These techniques are used, as has already been indicated, in a path in which lower order plesiochronous tributaries are combined to form a higher order channel. This higher order channel has its own fixed frequency clock, for which reason the differences with the corresponding tributary clocks are taken up by means of the justification mechanisms mentioned.
In the inverse process, in which there is a higher order channel from which several tributaries have to be obtained, there are other mechanisms that permit the net data streams to be maintained, at both the input and the output, for the correct operation of the digital transmission system.
These mechanisms are constituted by the use of "elastic memories" as explained in the book "Jitter in Digital Transmission Systems" by Patrick R. Trischitta and Eve L. Varma, published by Artech House with ISBN 0-89006-248-X, chapter 5, pages 103-139.
In this publication, FIG. 5.10 shows in graphical form how a tributary is obtained from a channel of higher hierarchical order in which there are two pointers, one for writing and one for reading, that operate cyclically on the same memory, in which the write pointer has control of the storage addresses of the input data entering this memory, and the read one has control of the read addresses for obtaining the output data.
The write pointer is formed by a cyclic counter that is incremented according to a write clock signal, which is blocked when bits are detected that do not belong to the tributary in question; that is, it detects path overhead, information from other tributaries, or else empty justification bytes or groups of eight justification bits, also empty.
In this way, though not with a steady flow, the memory holds, in a sequential and cyclic form, only the information bits of the corresponding tributary.
Simultaneously, the read pointer, which is another cyclic counter, is incremented in accordance with a read clock signal in order to proceed with the extraction of the information data of the corresponding tributary.
When, as a consequence of the tolerances in the read and write clock frequencies, small differences arise in these, then one of the two pointers would catch up with the other so that all the information entering the memory could not be read and there would be a loss, or else the amount of information read would be greater than that entering and there would be a loss of control of the available information.
To overcome this problem, a frequency control technique is used in the read pointer clock, as is shown in FIG. 5.10 of the publication mentioned.
This technique, as is explained, consists in obtaining a phase comparison signal, normally at 180.degree., from two signals obtained from the read and write pointers respectively, when these pass through a determined reference value for each case. This comparison signal is filtered and applied to a voltage controlled oscillator which serves to generate the clock signal with which the read pointer works. In this manner, if the read pointer, or data output, is delayed with respect to the write pointer, the read clock frequency is increased in order to compensate the delay.
Similarly, if the read pointer is fast, the read clock frequency is reduced to compensate the advance.
Nevertheless, despite the assurance that the net amount of information that leaves the memory is the same as that which enters, the relative leads and lags in the phase comparison signals mentioned, mainly due to the justification mechanisms, produce a phase noise or jitter which can surpass the permissible values according to the standards set for the Synchronous Digital Hierarchy.
Although at first sight it could be imagined that this can be achieved by narrowing the passband of the lowpass filter at the input to the voltage controlled oscillator, this would produce locking-on problems in the phase-locked loop circuit, and consequently this solution does not appear acceptable for this system.